AdmissionSetuAD
Hackathon prototype · Candidate, admission, document, vacancy, and seat states are synthetic. Official CET reference data is labelled.

Synchronized merit clearing

VIT Pune

Computer Engineering

LIVE
Synthetic clearing dataPositions use a simplified global merit rank. This is a proposed prototype model, not a statement of current CET policy.
Seats represented2exact synthetic seat records
Seats available2offered seats excluded
Your merit position#32 candidates ahead
Offers pending0limited by available seats

Deterministic demo event

Advance the VIT merit list

Two higher-ranked candidates confirm other choices. Aarya moves from #3 to the next offerable position.

Live merit list

Ranked candidate queue

6 active
  1. #1
    Candidate #1014Synthetic merit 401
    WAITING
  2. #2
    Candidate #1077Synthetic merit 438
    WAITING
  3. #3
    Aarya (you)Synthetic merit 463
    WAITING
  4. #4
    Candidate #2092Synthetic merit 478
    WAITING
  5. #5
    Candidate #2391Synthetic merit 519
    WAITING
  6. #6
    Candidate #2680Synthetic merit 566
    WAITING

Shared state

Clearing event log

  1. Merit clearing network openedSynthetic programme merit lists are ready.
Open technical operations view →
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