AdmissionSetuAD
Hackathon prototype · Candidate, admission, document, vacancy, and seat states are synthetic. Official CET reference data is labelled.

Synchronized merit clearing

PICT

Electronics and Telecommunication Engg

LIVE
Synthetic clearing dataPositions use a simplified global merit rank. This is a proposed prototype model, not a statement of current CET policy.
Seats represented3exact synthetic seat records
Seats available2offered seats excluded
Your merit position#43 candidates ahead
Offers pending0limited by available seats

Live merit list

Ranked candidate queue

7 active
  1. #1
    Candidate #1042Synthetic merit 412
    WAITING
  2. #2
    Candidate #1187Synthetic merit 427
    WAITING
  3. #3
    Candidate #2044Synthetic merit 441
    WAITING
  4. #4
    Aarya (you)Synthetic merit 463
    WAITING
  5. #5
    Candidate #2092Synthetic merit 478
    WAITING
  6. #6
    Candidate #2268Synthetic merit 502
    WAITING
  7. #7
    Candidate #2680Synthetic merit 566
    WAITING

Shared state

Clearing event log

  1. Merit clearing network openedSynthetic programme merit lists are ready.
Open technical operations view →
← All merit roundsPrototype operations view